Memory controllers can protect PC memory. Dynamic memory controller Basic states and modes of operation of the device

General principles of RAP organization. The DMA mode is the fastest way to exchange, which is implemented using special hardware - DMA controllers without the use of software. To implement the PDP mode, the controller must perform a series of sequential operations (Fig. 3.38):

DMA cycles are executed with sequentially located memory cells, so the DMA controller must have a RAM address counter. The number of PDP cycles is determined by a special counter. The exchange is controlled by a special logic circuit, which, depending on the type of exchange, generates a pair of control signals:
(read cycles),
(write cycles). It follows from the foregoing that the DMA controller, upon request, must take control of the system buses and perform combined read/output or write/input cycles until the content of the DMA cycle counter is equal to zero. On fig. 3.38 shows a block diagram of the MPS with a PDP controller.

The PDP controller K1810VT37 is used as part of the MPS based on the K580, K1810, K1821 MPCs to implement direct memory access via four independent channels with a positive or negative address increment at a speed of up to 1.6 MB/s. KDPP allows to implement memory-memory transfer, having wide possibilities of program control and cascading. Each channel can perform up to 64K DMA cycles and has the possibility of automatic initialization, i.e. repetition of DMA cycles with the same parameters.

Purpose of conclusions of KPDP(Fig. 3.39).

CLK– input for connecting the clock generator F CLK =3 MHz.

-Crystal selection.
permits the work of the KPPP.

RESET- reset. A high-level signal resets the RCAP by setting the instruction, condition, temporary storage registers to zero, and by setting all bits of the mask to one.

READY- readiness. The input signal used to synchronize the operation of the PDCA with slow-acting devices.

HLDA- Capture confirmation. The input signal used by the CPU to tell the RPCH that it can execute RPCH cycles.

DREQ3 – DREQ0 – inputs of requests to RAP from external devices. The polarity of requests is set programmatically. The signals at these inputs must be held until the DACK signal arrives. In the initial state, the request priority is natural, DREQ0 has the highest priority.

D.B.7 – D.B.0 – a bidirectional data bus with a z-state buffer. In DMA cycles, these lines are given the eight most significant digits of the address code, which must be “latched” onto the external register with the ADSTB signal. In the mode of operation with the CPU, these lines receive / transmit data.

-reading; how the input is used by the CPU to read the contents of the internal registers of the CPAP; as an output in DMA mode allows the output of data from external devices.

–record; how the input is used by the CPU to load data into the registers of the CPAP; as an output in DMA mode allows writing data to registers of external devices.

– end of the process. An input/output used to indicate the end of a data transfer process in DMA mode. By applying a low level signal to this input, you can stop the data transfer. After the data transfer is completed on one of the channels, a signal is set at the output
. On this signal (external or internal), the request is removed and the service is terminated. If the auto-initialization mode is set, then the working registers of this channel are loaded with the contents of the base registers, and the bits of the mask register do not change. In modes without autoinitialization, the mask bits and the TC bit in the status word are set according to the state of the served channel. When transferring memory - memory output
is oriented to the output, and at the end of the count, a signal is generated at this output. If output
is not used, it must be connected through a resistor to the power bus (+5 V) to prevent the formation of false signals of the end of the process.

A3 - A0 - address inputs/outputs. They are used as inputs in the CPU operation mode and for addressing the channels and registers of the channels of the RCAP. In DMA mode, they are outputs that carry the four least significant bits of the RAM address.

A7 - A4– address outputs, to which the corresponding bits of the RAM address are transferred in the DMA mode. In CPU mode, they enter the z-state.

HRQ– Tire grab request output. Request to the CPU to switch to DMA mode.

DACK3 – DACK0 - confirmation of the RAP. Output lines to which messages are issued for the VU about the possibility of performing DAP cycles. The polarity of the signal is set by software. After the RESET signal, the DACK outputs are set to zero.

AEN- address resolution. AEN=1 is set at the time of issuing the eight most significant bits of the RAM address on line DB7 - DB0.

ADSTB– address strobe. The output on which a pulse (strobe) is generated that writes the high-order bits (A15 - A8) of the RAM address from the DB7 - DB0 buses to an external buffer register.

- reading from memory. An output used in DMA mode to control a memory read operation.

- write to memory. An output used in DMA mode to control a memory write operation.

U cc– power bus (+5 V).

GND- general.

Structure of the CPAP(See Figure 3.39). The controller includes four channels, each of which consists of four 16-bit registers.

Register current addressCAR stores the current address of the memory cell during the execution of the DMA cycle. After the DMA cycle is completed, the contents of this register are incremented or decremented by one. It can be read or loaded with two I/O commands. CAR content can be updated on signal
, if the auto-initialization mode is programmed.

Register of PDP cyclesCWR stores the number of words to be transmitted. When loading this register, remember that the constant being loaded must be one greater than the number of words needed to transfer. When performing DAP cycles, the register operates in the subtractive counter mode. The TC bit of the status register is set to one on the transition from the zero state to the FFFFH state. Reading and writing the contents of the register is carried out by two sequentially executed input-output commands. The contents of the CWR can be updated by signal auto-initialization
or the value FFFFH is stored in the register.

Base address storage registerBARand the storage register for the basic number of DAP cyclesWCR store the basic values ​​of the address and the number of DAP cycles, participate in auto-initialization. During the initial loading of the PMA controller with initial parameters, the CAR, BAR, CWR and WCR registers are simultaneously written. During the execution of the PDP cycles, the contents of BAR and WCR do not change. It is impossible to read the state of these registers.

In addition, each channel has a 6-bit mode registerMR, which determines the mode of its operation. When this register is loaded, the least significant bits of D1, D0 indicate the channel number code. The assignment of the MR bits is shown in fig. 3.40.

With the help of bits D2, D3, one of the types of transmission is specified - reading, writing, checking. These bits can take any value when D6D7=11. Bit D4 determines the autoload mode. If D4=1, then under the autoload condition CAR and CWR are loaded by parameters BAR and WCR respectively. The D5 bit determines the CAR change mode. If D5=0, after each RAP cycle, an increase in the content of the CAR occurs; if D5=1, then there is a decrease. Bits D6, D7 determine the channel operation modes - transmission on request, single transmission, block transmission, controller in cascade mode.

The PMA controller includes three functional blocks that perform control functions. Data bus buffer serves to coordinate the operation of the controller with the CPU. Some of the signals that provide these functions are used to control the transmission of data in DSP cycles. Controller control unit when transferring memory - memory includes one 8-bit register TR temporary data storage, which provides storage of a byte in the transfer cycle memory - memory for the time of changing the address.

The word last loaded into this register is stored there until a RESET signal is received. PDP mode control unit generates the necessary control signals when transmitting data in DMA cycles. Includes two 8-bit and two 4-bit registers.

Command registerCR determines the main parameters of the channel. The CR is loaded by an output command from the CPU, and reset by a RESET signal or a general reset command. The purpose of the register bits is shown in fig. 3.41. Bits D0, D1 are used to set the operating modes of channels 0 and 1 in the memory-memory mode. Bit D2 initializes the controller to perform DMA, bit D3 determines the mode of execution of DMA cycles. If D3=1, DMA cycles are executed with one clock skip when the address changes within the low byte. Bit D4 sets the priority mode. If D4=1, the service channel request is assigned the lowest priority - priority rotation mode. Bit D5 sets the extended write cycle mode. If D5=1, signals
produced with double duration. Bits D6, D7 program the levels of requests for DMA (DREQ) and DMA confirmation signals (DACK).

Condition registerSR. Bits D3 - D0 of this register are set by hardware when a TC signal occurs, i.e. after the end of DMA cycles or by an external signal
. These bits are reset (set to zero) by the RESET signal and after the command to read the contents of this register is executed. Bits D4 - D7 are set by software if service is required on the corresponding channel. The assignment of the SR bits is shown in fig. 3.42.

Request RegisterRR. The controller can serve requests for DMA generated both by hardware - by DREQ inputs, and by software - by the state of bits (registers) of RR requests. Each bit of this register corresponds to a request on one of the channels. The bits of this register are not masked and are set separately by software or signals TC and
. The software setting of these bits is carried out by the command, the format of which is shown in Fig. 3.43. All RR bits are reset by the RESET signal. To process a program request, the controller must be programmed in block transfer mode.

Mask caseMASK, with which the DREQ signals of each channel can be masked. The MASK bits can be set by a special command simultaneously (Fig. 3.44) or separately (Fig. 3.45). In addition, if the channel is not programmed for autoload mode, after the signal
the corresponding bit of the register is set to one. All MASK bits are set to zero by the RESET signal or by the CMR (Clear Mask Register) command.

PDP operating mode. The DMA controller can operate in two main modes: with the CPU and performing DMA cycles. In the mode of operation with the CPU, the controller is perceived by it as an external device, and after loading the control words it goes into the passive state S1. The controller stays in this state until a request for a DREQ DMA is received at the input of one of the channels or this request is set by the CPU programmatically. Upon detecting a DMA request, the controller enters the S0 state and asserts the HRQ system bus capture request signal, waiting for the HLDA capture confirmation signal from the CPU. When the HLDA signal is received, the controller begins to execute DMA cycles.

There are four operating states during these cycles: S1 - S4. If, during the execution of DMA cycles, a zero is applied to the READY input, the controller performs SW waiting cycles between cycles S2/S3 and S4. The SW state is characterized by the activity of the data lines. When transferring information in the memory-memory mode, it is necessary to perform two complete read and write cycles, therefore, to transfer one word, the controller performs two DMA cycles of four cycles each: S11 - S14 for reading from memory and S21 - S24 for writing to memory.

The timing diagram of the controller operation in PDP cycles is shown in fig. 3.46. In the passive state, the request inputs to the RAP are polled and interaction with the CPU is possible using the usual input-output commands. Since the interaction with the CPU is more often carried out by a word of two bytes, the controller uses an internal trigger to select them correctly, indicating an operation with the low or high byte of the word. This flip-flop is reset by a RESET signal or a general reset command, indicating a low byte operation. After performing an operation on the low byte, it is set to one, indicating the high byte.

The controller can be programmed to perform the following four DMA modes of operation. In single transmission mode one byte is transmitted, while the contents of the DMA cycle counter (CWR) are decremented, and the contents of the address register (CAR) are decremented or incremented by one. The Transmission End (TC) bit in the Condition Register is set to one when the contents of the CWR are set to FFFFH. The DREQ input must be kept active until the DACK signal arrives. If DREQ remains active after one byte has been transmitted, the HRQ signal is removed, and a new transmission cycle is possible with the arrival of the next HLDA signal.

In block transfer mode DMA cycles are performed until the TC bit in the condition register is set, i.e. when the DMA cycle counter CWR takes the value FFFFH or the transmission is stopped by an external signal
. Transmission cycles can be resumed if the channel has been programmed to auto-initialize.

In On-Demand mode DMA cycles continue until the TC bit in the condition register is set or the signal
, or the DREQ signal is not deasserted.

In this mode, transmission can be carried out until the external device completes the transmission of information. Auto-initialization in this mode can be performed after the end of signal transmission
, external or produced on the basis of TC.

Memory-to-memory transfer mode allows you to move blocks of information in the field of RAM. To implement this mode, the parameters of channels 0 and 1 are used. The transmission is initialized by software by setting DREQ in channel 0. After the arrival of the HLDA=1 signal, the controller reads data from the memory cell with the address from the CAR register of channel 0 in four cycles and writes them to the temporary storage register TR , and then, in four cycles, writes this data to a memory cell with an address from CAR channel 1. When the contents of the DMA cycle register CWR takes on the value FFFFH, the TC bit will be set and the transfer will end. Channel 0 can be programmed to transmit information without changing the address, which allows you to fill the cells of the RAM block with a constant.

Types of RAP transmission. In all DMA modes, three main types of transmission are possible. Data recording– carried out transferring data from an external device to RAM. The controller in this case activates the signals
.Reading data– data is being transferred from the RAM to an external device, signals are activated
. When checks or pseudo-transfers the controller performs the same actions as in the read / write cycle, but no control signals are generated. In this case, the READY signal is not accepted. In addition, the controller can be programmed to perform additional functions.

Auto initialization is carried out if the corresponding bit is set in the condition register, and by a signal
. During auto-initialization, the contents of the base registers BAR and WCR are loaded into the current value registers CAR and CWR. The bits of the mask do not change. After auto-initialization, the controller is ready for operation and resumes operation with the arrival of the next DREQ signal. For auto-initialization of both channels in the memory-memory mode, the CWR DMA cycle registers must be programmed identically.

The controller can be programmed to serve channels with hard set priorities either from their cyclic change. With a hard-coded priority, the highest priority is given to the channel with the lowest number. In wraparound, the lowest priority is given to the channel after it has been serviced. This allows you to serve all channels in turn.

Table 3.3

Controller programming. Controller programming is carried out from the CPU by I/O commands and is possible only in the passive state or if there is a low level voltage at the HLDA input, even if the HRQ signal is present. The initial initialization of the controller must be carried out immediately after switching on the supply voltage for all channels (even if they are not used), loading commands and constants. The addresses of the internal registers of the controller are determined by the code on pins A3–A0. Table 3.3 shows the codes on A3–A0, corresponding to the executed CPU commands, and in Table 3.4, the codes on A3–A0, corresponding to the addresses of the KPDP registers.

Table 3.4

Connecting the controller to the system bus(Fig. 3.47). The most significant eight bits of the address are issued to the stepper motor and must be written by the ADSTB signal to an external register. The AEN line is used to ensure that the address bits remain valid on the SHA for three clock periods of the DMA cycle. Lines A7 - A0 are connected directly to the SHA. The signals MEMR, MEMW, IOR, IOW control the RAM and the VU buffer in the DMA cycles, respectively.

Cascading KPDP. An example of a cascaded use of the PDCA can be an IBM PC / AT, in which a second 8237A was connected to the address bus with an offset of 1 byte (Fig. 3.48). Its 16-bit address registers are capable of driving address lines A16 - A1 (the low byte of A0 is always 0). Thus, the second PDCH provides transmission of two bytes. The second 8237A chip is connected as master and creates three 16-bit DMA channels.

Questions and tasks

3.37. What are the operating modes of the KPPP and its functions in the system?

Define software-accessible registers and their addressing.

Make a diagram of connecting K1810BT37 to the address and data buses of the MPS.

Compose a controller initialization program for block exchange over one channel.

Explain the implementation of the PDP mode on VT37.

Explain the addressing of the KPDP registers when programming.

How is the 16-bit address of the RCAP formed during exchange control?

Explain the provision of RRPs upon requests from a slave RPCS.

What request priorities does the 8237 (BT37) support?

In what sequence is it necessary to load the controller registers when programming it?

The Embedded Flash Controller (EFC) is part of the Memory Controller (MC) and provides an interface to access flash memory blocks over an internal 32-bit bus. This allows you to significantly increase the speed of fetching instructions from flash memory when the processor core is operating in the Thumb mode (16-bit instruction system) due to the operation of the 32-bit buffer. Moreover, the embedded flash controller supports a full set of commands for reading, writing, erasing flash memory, setting and clearing security bits.

20.2 Functional description

20.2.1 Organization of the built-in flash memory

The on-board flash memory interfaces are directly connected to an internal 32-bit bus based on several of the following interfaces.

• Simple memory organization: multiple pages of the same size.
• Two 32-bit read buffers designed to increase flash read speed (see "Read Commands" on page 101).
• One write buffer to store data when programming one flash page. This buffer is the size of one page and is write-only. In addition, the write buffer addresses the entire 1 MB area of ​​flash memory (see "Write commands" on page 101).
• Several security bits (lock bits) to prevent erasing and writing of flash memory. Each protected area of ​​flash memory (all areas are of the same size) consists of a fixed number of pages placed sequentially. Each one such area is directly associated with only one security bit.
• A few bits of non-volatile memory - NVM (Non Volatile Memory) bits for general purposes. Each of these bits is responsible for controlling certain nodes of the microcontroller. For more information about each NVM bit, see the relevant chapters of this document.

Table 20-1. Number of Security Bits and General Purpose NVM Bit for AT91SAM7S Family Members

Figure 20-1. Built-in flash memory map

20.2.2 Read commands

To speed up the process of reading flash memory, a dedicated 32-bit buffer is built into the EFC controller. Due to the presence of this buffer, when the processor is operating in the Thumb mode (16-bit instruction system), access to flash memory occurs twice as rarely, due to which it increases the instruction fetch rate and, consequently, increases the speed of the processor (Fig. 20-2, Fig. 20-3 and Fig. 20-4).

This optimization is performed only when fetching instructions, and not when reading data from flash memory.

Read commands can be executed with or without additional wait cycles. Only up to three (inclusive) wait cycles can be set in the FWS (Flash Wait State) field of the Flash Mode Register MC_FMR (see "Flash Mode Register", page 110). With FWS = 0, the built-in flash memory is accessed in one cycle.

Flash memory access is available in 32-bit (dictionary), 16-bit (half-word), and 8-bit.

Since the size of the built-in flash memory is smaller than the microcontroller than the size of the address space of the internal memory allocated for it (1 MB), the memory controller implements the so-called. duplication of this block of flash memory throughout the address space allocated for it. For example, for the AT91SAM7S64, the 64KB flash memory is mapped exactly 1024/64 = 16 times in this address space.

Figure 20-2. Optimization when reading command code in Thumb mode for FWS = 0

Figure 20-3. Optimization when reading command code in Thumb mode for FWS = 1

Figure 20-4. Optimization when reading command code in Thumb mode for FWS = 3

20.2.3 Write commands

The internal memory area reserved for the built-in flash memory can also only be written to via a dedicated buffer. When executing flash write commands, only the lower 8 bits of the address are taken into account (since we are talking about 32-bit data, the 10 lower bits of the address are actually taken into account). In turn, the upper 10 bits of the address of the internal area (1 MB) reserved for flash memory address this so-called. a window that is 256 words (1024 bytes) in size. Thus, all this internal memory consists of 1024 such windows.

Any write command to the built-in flash memory can be disabled by the MPU (Memory Protection Unit).

Flash memory can only be written to in words (32 bits), so any attempt to write half words (16 bits) or bytes (8 bits) will produce an unpredictable result.

Write commands take the number of wait cycles (FWS field in MC_FMR) specified for read commands, plus one extra cycle, except when FWS = 3 (see "Flash Mode Register", page 110).

20.2.4 Flash controller command set

EFCS includes commands for programming flash memory, commands for setting protection (unprotecting) its areas, commands for sequential programming and setting flash memory protection, and a command for completely erasing all flash memory.

Table 20-2. Flash Controller Command System

Before executing any of these commands, the FCMD field of the MC_FCR register must be set to the code for that command. Since MC_FCR is read-only, the FRDY flag is automatically cleared. After the instruction has finished executing, the FRDY flag is automatically set, which can trigger the corresponding interrupt if enabled via the memory controller (MC).

All flash instructions are protected from accidental execution by using one common keyword (keyword), which must be specified in the upper 8 bits of the MC_FCR register each time the next instruction is executed.

An instruction with an incorrectly specified keyword and/or an incorrectly specified code for that instruction will not be executed, even if the PROGE flag in the MC_FSR register is set. This flag will be automatically reset the next time the MC_FSR register is read.

An attempt to write or erase a page located in a protected area will have no effect on the contents of flash memory (in fact, this command will be ignored), even if the PROGE flag in the MC_FSR register is set. This flag will be automatically reset the next time the MC_FSR register is read.

Figure 20-5. Command flowchart

For correct execution of flash commands, the Cycle Time in Microseconds (FMCN) field in the Flash Controller Mode Register (MC_FMR) must be set to the correct value (see "Flash Controller Mode Register", page 110).

20.2.4.1 Flash programming

Just a few commands can be used to program flash memory.

According to the technology of flash memory, it must be erased immediately before the process of programming it. Either an entire flash area or an individual page can be erased by clearing the NEBP flag in the MC_FMR register directly by writing an instruction code to the MC_FCR register.

By setting the NEBP flag in the MC_FMR register, a page can be programmed in a certain number of steps if it has already been cleared beforehand (see Figure 20-6).

Figure 20-6. Example of Programming a Flash Page Section

After the end of the programming process, the page can be protected from accidental or intentional erasure or writing (when the entire area that this page belongs to is protected). Using the WPL command, protection can be set automatically immediately after the end of a page write cycle.

Written data is stored in an internal buffer, the size of which is equal to the size of one flash page. This internal buffer spans the entire address space of the internal flash, i.e. in fact, it can be displayed in its entirety on any of its pages.

Note: writing bytes (8 bits) or half words (16 bits) is prohibited, because as it causes corruption of the recorded data.

The process of writing data to flash memory previously allocated in the internal buffer is controlled by the flash command register (MC_FCR). Below is the sequence of work with this register.

• An entire page write, which can be placed at any address within the entire flash address space, is only possible as a dictionary (32-bit data).
• The page write cycle begins immediately after the page number and the write command code itself are specified in the MC_FCR register. This automatically clears the FRDY flag in the Flash Programming Status Register (MC_FSR).
• Immediately after the completion of a programming cycle, the FRDY flag is set in the Flash Programming Status Register (MC_FSR). If interrupts from the FRDY flag are enabled, then the appropriate interrupt signal will occur in the memory controller (MC).
• Programming Error: An invalid keyword was written to the MC_FSR register and/or an invalid command was specified.

20.2.4.2 Full Erase Flash Command

All on-chip flash memory can be erased if the MC_FCR register is written with the "Erase All" command - EA (Erase All).

Erasing the entire flash memory is possible only when none of its areas is protected from erasing and writing (not one of the flash memory protection flags is set). Otherwise (at least one of the protection flags is set) this command will be ignored. If the LOCKE flag in the MC_FMR register is set, the corresponding interrupt signal will occur.

The FRDY flag will automatically be set in the MC_FSR register after the last programming command or flash memory is erased. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

During the execution of the programming cycle, errors may occur that are recorded in the MC_FSR register. These errors are listed below.

• Programming Error: An invalid keyword was written to the MC_FSR register and/or an invalid command was specified.
• Lock Error: An attempt was made to program a secure area. To program this area correctly, it must first be unprotected using the unprotect command.

20.2.4.3 Flash protection bits

Each of the security bits is tied to a specific area of ​​flash memory, consisting of a specific number of pages. The purpose of these bits is to protect the flash memory from accidental or intentional erasure/programming.

During the manufacturing process of the microcontroller, some of the protection bits may be set in it. Their purpose is to protect a certain area of ​​flash memory, which by default contains a program written to the microcontroller during its production. Before programming/erasing a protected area, it must be unprotected.

The following is the order in which protection for one area is set:

The following value should be written to the flash command register: (0x5A after the completion of the protection command, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled. ul>

After the protection is set, it can be unprotected, the following is the sequence of unprotecting one area:

• The following value should be written to the Flash Command Register: (0x5A, after the execution of the protection command, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

If an error occurs during command execution (an invalid keyword and/or an incorrect command code is specified in the MC_FCR register), then this fact will be recorded in the MC_FSR register.

Executing the command to clear a lock bit physically writes a "1" to the corresponding bit, although reading the MC_FSR register reads the corresponding LOCKx bit as a "0". Conversely, executing a lock bit set command physically writes a "0" to the corresponding bit, and reading the MC_FSR register reads the corresponding LOCKx bit as a "1".

Note: regardless of whether the flash memory is protected, it can still be accessed by reading.

20.2.4.4 General purpose NVM bits

General purpose bits - NVM bits - are not associated with the built-in flash memory, but are intended to protect other nodes of the microcontroller. Each of these bits can be set (cleared) independently of the others. For details about NVM bits, see the relevant chapters of this document.

The following is the activation sequence for the general purpose NVM bits.

• Execution of the Set General Purpose NVM Bit (SGPB) command by writing to the Flash Memory Command Register (MC_FCR) the code of this command and the number of these bits in the PAGEN field of the same register.
• after the completion of the SGPB instruction, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

During the execution of the programming cycle, errors may occur that are recorded in the MC_FSR register. These errors are listed below.

• The PAGEN field of the MC_FCR register indicates the number of general purpose bits that is greater than the maximum allowed number of NVM bits implemented in the chip. Following is the sequence for clearing the general purpose NVM bits.
• Execution of the Clear General Purpose NVM Bit (CGPB) command by writing to the Flash Memory Command Register (MC_FCR) the command code and the number of these bits in the PAGEN field of the same register.
• when the CGPB instruction completes, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

During the execution of the programming cycle, errors may occur that are recorded in the MC_FSR register. These errors are listed below.

• Programming Error: An invalid keyword was written to the MC_FSR register and/or an invalid command was specified.
• The PAGEN field of the MC_FCR register indicates the number of general purpose bits that is greater than the maximum allowed number of NVM bits implemented in the chip.

Executing a "clear NVM general purpose bits" command physically writes a "1" to the corresponding bit, although reading the MC_FSR register reads the corresponding GPNVMx bit as a "0". Conversely, executing a "Set General Purpose NVM Bits" command physically writes "0" to the corresponding bit, and reading the MC_FSR register reads the corresponding GPNVMx bit as "1".

Note: regardless of the state of the general purpose NVM bits, flash memory is always readable.

20.2.4.5 Security bit

The secret bit is intended to prevent external attempts to access the internal system bus. After setting the security bit, the operation of the JTAG interface, the flash memory fast programming interface and access to the flash memory via the serial interface is prohibited. Access to flash memory via the above interfaces is again allowed only when the crystal is completely cleared via the external ERASE pin - see chapter 4. "Pin Assignment". When the ERASE pin is driven high (see section 7.4. "Erase control pin"), all on-chip flash, all flash protection bits, and all general purpose NVM bits are cleared, and only after all this is done clearing the privacy bit.

The sequence for setting the privacy bit is given below.

• Execute the Set Security Bit (SSB) command by writing the command code to the Flash Command Register (MC_FCR).
• after the completion of the SSB instruction, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

Immediately after setting the security bit, the SECURITY flag will be set in the MC_FSR register.

Processor core of microcontrollers:
– arithmetic logic unit
- organization of memory

Good day dear radio amateurs!
I welcome you to the site ""

Today (more precisely, in the course of several articles), we will take a closer look at basis any microcontroller – processor core.

Main elements:

1. Arithmetic logic unit

ALU- the heart (and maybe the mind, with honor and conscience) of the microcontroller.
Here we will not enter into the role of a “maniac dismemberment” and poking around in the insides of this device. We only learn that thanks to the ALU, all the work of the microcontroller takes place. If you ever have a desire to learn more deeply how the “heart” of the microcontroller works (and it will be nice if it appears), then in the books of the wonderful authors Belov, Ryumik, Evstifeev, Revich, Baranov and many others, you will always find a detailed answer .

2. Microcontroller memory (memory organization)

Before considering the memory of the microcontroller, let's talk a little about memory in general.
Human memory - everything is clear with it - it can be “solid” (when you are in a solid memory, and sometimes even in your right mind) and, sadly, “leaky”. And all the information is stored in the so-called "neurons" - small memory cells.
Almost everything is the same with microcontrollers. Only if a person has the smallest cell for storing information called a “neuron”, then the smallest memory cell for a microcontroller to store information is called " bit“.
One bit can store either one logical one or one logical zero.
Bit – the minimum unit of measure for the amount of memory in microprocessor technology.
The next major, or most common, unit of memory is byte.
Byte – that's eight bits of information. One byte can store only eight zeros and ones.
The maximum number that can be written into a byte is 255. If you operate with large numbers in the program, then you should know (in order to know how many bytes are required to store the number) that the maximum number that can be written to:
– one byte = 255
– two bytes = 65535
– three bytes = 16 777 215
- four bytes - a number larger than 4 billion (if you are not at least one hundred of the Forbes magazine, then you will not need four bytes of memory to store numbers).
Writing to memory and reading from memory occurs in bytes (you cannot write or read one bit of information).
The next unit of measure is kilobyte.
There are 1024 bytes of information in a kilobyte. (exactly 1024, not 1000 bytes).
There are also large values ​​for measuring the amount of memory (megabytes, gigabytes), but they are not yet used in microcontrollers.
I hope that everything is clear to us with the units of measurement of electronic memory:

Organization of memory in the microcontroller

AVR chips have three types of memory:
– program memory, aka FLASH memory
– data memory, aka RAM (RAM)aka SRAM
– non-volatile memory, aka EEPROM, aka EEPROM
The microcontroller has three address spaces in which the above types of memory are located. At the same time, the data memory (in terms of allocated address space) turned out to be a little deprived - it has to share its address space with memory cells that store general-purpose registers and I / O registers (you will learn about them in detail in the next article). These registers do not physically belong to data memory, but are in the same address space. If the starting addresses of program memory and non-volatile memory start at address zero, then the start address of data memory does not start at address zero - general-purpose registers and I/O registers take their places from address zero, and only they are followed by addresses of program memory cells.
Some types of ATiny MCUs do not have data memory.

Program memory (FLASH memory)

Program memory is designed to store our programs in it, as well as any data we need that do not change during the execution of the program (constant). When the power of the microcontroller is turned off, all data in the program memory is saved.
Program memory, of course, have all microcontrollers. The size of the program memory, depending on the type of MK, varies from 1 kilobyte to 256 kilobytes.
Program memory access only the programmer has when programming the MK, the MK itself also has access to the program memory, but only to read data from the memory, it cannot write anything there (you never know, it suddenly wants to spoil our program). True, the MK of the Mega family has the opportunity (with the permission of the programmer) to make changes in the program memory, but this is a different story.
For program memory, there are two more types of memory measurement - “ word" and " page“.
The fact is that program memory consists of cells consisting of two bytes. Such a cell is called a "word". And this is done this way because almost all MK commands consist of two bytes, and, accordingly, two bytes are needed in the program memory to write them. Each MK command is one “word”. There are several commands that require 4 bytes of memory to write - two words, but such commands are found in MKs with program memory greater than 8 kilobytes.
Thus, in one cell of program memory can be written:
- any command consisting of two bytes
- half of the command, consisting of 4 bytes
- two constants, each of which fits in one byte, or one sixteen-bit constant. However, if you write three one-byte constants to memory, they will still occupy four bytes (two words) in memory.
Besides, writing to the program memory is carried out not only by “words”, but also by “pages” . Page Size is from 64 to 256 bytes (the larger the amount of program memory, the larger the “page”). What does it mean. If you have created a small program that is 11 words (22 bytes) long, it will still take up one page of program memory, i.e. at least 64 bytes. The “extra” 42 bytes will be filled with either zeros or ones. These are the pies.
But that's not all.
Program memory can have three states(if I may say so):
1. All memory is at the disposal of the programmer
In this case, we can fill all the memory completely with our program and data. And the program will start from the zero memory address.
2. Part of the memory takes MK
In the event that MK is used during operation (and I hope you remember what it is), the MK takes part of the memory for the needs of interrupt processing and stores it in it “ interrupt vectors“.
What it is.
When we allow the MK to process interrupts, it, starting from the zero address of the memory, takes some of the cells to store the addresses in them, which the MK must go to to execute the interrupt routine. For each interrupt, the MK allocates two bytes of memory (one word) that store the addresses of the interrupt routines. These addresses, which indicate where the subroutine for processing this or that interrupt is located in memory, are called “ interrupt vectors“. And the entire area of ​​\u200b\u200bmemory in which “interrupt vectors” are stored is called interrupt vector table. The number of occupied memory cells for interrupts depends directly on the number of possible interrupts of a given microcontroller (from a few to several dozen). All interrupts are located at the beginning of the program memory, from address zero, and have a clear sequence. At address zero, the reset interrupt vector is always located. When we turn on the device, or reset with the button, the reset interrupt is triggered. The MK reads from the zero address (from the cell) the address that indicates where in memory the beginning of our program is located, and by going to this address it starts executing the program. The program itself in this case will be located in the program memory immediately after the interrupt table.
3. MK takes another part of the program memory (more precisely, it does not take, but allocates an area at the end of the memory, in which the programmer places a special program - the “loader”).
This is possible in MCUs of the “MEGA” family, which have the ability to allow the MCU to make changes to the program memory. What does it mean.
Some MKs have the ability self-program. In the practice of amateurs, this possibility of MK is used extremely rarely. The ability to reprogram (self-program) is needed mainly in cases of industrial production of a device on a microcontroller, for which a software update can then be released. We will not consider this possibility, at least not yet. We just need to know that in MKs that support self-programming, the program memory is divided into two parts :
- upper - application program section, where our program is located and interrupt vectors
- lower - bootloader section (Boot Loader Section- in English), where the programmer places his loader program. The size of the bootloader section depends on the total size of the MK program memory, and can range from 128 bytes to 4096 bytes. If we do not use the possibility of self-programming of the MK, then this section is given for our program and data.
Well, FLASH memory is called program memory because it is made using the so-called Flash technology (like the usual computer “flash drives” for all of us).
The program memory allows 10,000 reprogramming cycles.

Data Memory (Static RAM, SRAM)

RAM, it is data memory type SRAM, designed to store in it various data obtained as a result of the program.
When the power of the microcontroller is turned off, all data stored in it is lost.
Data memory is available in almost all microcontrollers (absent in the simplest MKs of the Tiny family).
In all MCs of the Mega family (and part of the MCs of the Tiny family), the amount of built-in data memory ranges from 128 bytes to 8 kilobytes, and almost all of it is given to our full disposal. It only takes a little MK for itself to organize the stack (we will find out what it is later). Some MKs provide for the connection of external memory (it can be of any type - FLASH, SRAM, EEPROM) up to 64 kilobytes. In the case of connecting external memory in such MKs, it becomes, as it were, a continuation of the data memory.
Writing to and reading from data memory occurs byte by byte, and unlike program memory, it is not divided into pages and words.

Non-volatile memory (EEPROM)

Non-volatile memory also refers to data memory, but unlike the latter, it has several features. It is intended to store data and constants that must be preserved in the absence of power.
All microcontrollers have EEPROMs.
When the power of the microcontroller is turned off, all data stored in the non-volatile memory is saved (which is why it is called non-volatile).
The amount of non-volatile memory, depending on the type of MK, ranges from 64 bytes to 4 kilobytes.
Writing and reading information into memory is done byte by byte. However, in the older models of the MEGA family, non-volatile memory, as well as program memory, has a page record. The page size is small, only 4 bytes. In practice, this feature does not matter - both writing and reading are still carried out byte by byte.
Number of write and erase cycles memory reaches 100,000.
The main feature of EEPROM is that when data is written to it, it becomes very “slow” - writing one byte can last from 2 to 4 milliseconds (this is a very low speed), and it can happen, for example, that some - or interruption, in which case the data writing process will be ruined.
In addition, it is not recommended to write data to non-volatile memory from address zero (I don’t remember the source of this information, but I remember exactly what I read somewhere) - data may be damaged during the operation of the MK. Sometimes programmers step back a few bytes from the beginning of memory, and only in the next cells do they start writing data.

Today in the civilized world you will hardly find a person who has never used a computer and has no idea what it is. Therefore, instead of once again talking about the well-known parts of this complex system, we will tell you about something that you do not yet know. We will discuss and give a short description of the memory controllers, without which the operation of the computer would be impossible. If you want to understand the system of your personal computer or laptop, then you must know this. And so, let's discuss today what memory controllers are.

The task that the computer's memory controllers face is very important for the operation of the computer. The memory controller is a chip that is located on the motherboard or on the central processing unit. The main function that this tiny chip performs is to control the flow of data, both incoming and outgoing. The secondary function of the memory controller is to increase the potential and performance of the system, as well as the uniform and correct placement of information in memory, which is available thanks to new developments in the field of new technologies.

The location of the memory controller in your computer depends on certain models of motherboards and CPUs. In some computers, the designers have placed this chip on the north parallel connection of the motherboard, while in other computers they are placed on the "die" CPU. Those systems that are designed to install the controller in the motherboard have a large number of new different physical sockets. The RAM used in this type of computer also has a new modern design.

The main purpose of using a memory controller in a computer is to allow the system to read and write changes to RAM and update it on every boot. This is due to the fact that the memory controller sends electrical charges, which, in turn, are signals to perform certain actions. Without delving into technical terminology, we can state the fact that memory controllers are one of the most important parts in a computer that allow the use of RAM, and without which its work would be impossible.

Memory controllers come in different types. They differ in:
- memory controllers with double data transfer rate (DDR);
- fully buffered memory controllers (FB);
- two-channel controllers (DC).

The functions that different types of memory controllers can perform differ from each other. For example, dual baud rate memory controllers are used to transfer data, depending on the increase or decrease of the memory clock rate. Whereas dual-channel memory uses two memory controllers parallel to each other. This allows the computer to increase the speed of the system by creating more channels, but despite the difficulties that come from using a bunch of wires, this system works quite efficiently. However, there are difficulties when creating new channels, so this type of memory controller is not perfect.

Fully buffered memory controllers, on the other hand, are different from other types of memory controllers. This technology uses serial data channels that are needed to communicate with the motherboard and unlike other systems, RAM memory circuits. The advantage of this type of controller is that fully buffered memory controllers reduce the number of wires that are used in the motherboard, and thus reduce the time spent on the task.

As you have already seen, memory controllers are very necessary for the stable operation of the computer, and different types are used for different purposes. Prices for memory lines range from very high to very low, depending on the type and functions that a particular memory controller performs.

Typically, an industrial controller consists of: a central processor, network interfaces, memory modules, and various I/O devices.

The PLC processor module includes the following components: microprocessor or CPU (central processing unit), real time clock, memory devices and watchdog.

The main characteristics of the microprocessor include: clock frequency, bit depth, support for ports for various I / O devices, architecture, performance parameters for certain temperature ranges, floating point operations, power consumption level.

The performance of microprocessors with the same architecture is proportional to the clock speed. Most controllers use microprocessors implemented on the RISC (Reduced Instruction Set Computing) architecture, which have a reduced number of instructions. In this case, the microprocessor uses a certain number of instructions that have the same length, and many registers. Thanks to a reduced set of instructions, it is possible to create compilers with high efficiency indicators, as well as a processor pipeline that can produce the result of executing the actions of one of the instructions in one cycle.

Math-intensive industrial controllers require a math coprocessor (an auxiliary processor that performs floating point operations) or the use of signal processors that perform math operations for one clock cycle. Thanks to signal processors, a significant acceleration of convolution or fast Fourier transform operations is achieved.

The memory capacity is characterized by the number of variables that can be processed during the operation of the PLC. Microprocessor memory access time is one of the most significant indicators that can limit performance. Because of this, memory is divided into hierarchical levels, taking into account the frequency and speed of use of the data available in it. The memory hierarchy is another significant indicator of the processor architecture that allows you to reduce the level of possible negative impact of slow memory on the speed of the microprocessor.

The main types of memory for industrial controllers (PLCs):

• ROM - Read Only Memory;
• RAM - random access memory;
• Register set.

A set of registers are the fastest memory elements, as they are used by the ALU (arithmetic logic unit) to execute the simplest processor instructions. ROM is used as a place to store information that rarely changes - the operating system, bootloader, device drivers, or the executable module of a program. RAM stores data directly that is subject to multiple changes during the operation of the controller. For example, information about diagnostics, variables displayed on the display, tag values, intermediate calculations, data displayed on graphs. The role of ROM (ROM - Read Only Memory), as a rule, is reprogrammable electrically erasable memory (EEPROM - Electrically Erasable Programmable ROM). By the way, flash memory is essentially a kind of EEPROM. Its principle of operation is to store a certain charge in a capacitor, which is formed by a MOSFET substrate and a floating gate. The main feature of flash memory is its absolute non-volatility, i.e. the ability to save data in the absence of power. Updating data in flash memory does not occur in individual cells, but through the use of large blocks. All ROMs have a big drawback - a low level of performance.

The number of cycles of entering information into flash memory is limited to only a few tens of thousands of times. Modern microprocessors use static memory (SRAM - Static Random Access Memory), dynamic memory (DRAM - Dynamic Random Access Memory), and synchronous dynamic memory (SDRAM - Synchronous DRAM) as RAM. SRAM execution occurs on flip-flops that are capable of storing information indefinitely, provided that power is available. The dynamic memory of an industrial controller stores its data on capacitors, which requires periodic recharging of the capacitors. The main disadvantage of trigger memory is the high level of cost and price-to-capacity ratio. This is due to the fact that a relatively small number of flip-flops can be placed on one chip. The advantages include a high level of performance, calculated in gigahertz, while capacitor memory cannot overcome the bar of several hundred hertz. All types of RAM differ in that in the absence of power, all the information available in them is not stored. This is why some types of PLCs use battery power to keep the system running if there is a brief power interruption to the system.

Modular and monobloc industrial controllers use a parallel bus to communicate with I/O modules, resulting in significantly faster polling performance than a serial bus. Types of parallel buses: VME, PCI, ISA, CXM, ComactPCI, PC/104. A serial bus, such as RS-485, is required to connect remote I/O modules.