Study of logical elements. Study of the logic of work. logical elements. Brief information from the theory

To describe the operation algorithm of logic circuits, the mathematical apparatus of logic algebra is used. The algebra of logic operates with two concepts: the event is true (logical "1") or the event is false (logical "0"). Events in the algebra of logic can be connected by two operations: addition (disjunction), denoted by the sign U or +, and multiplication (conjunction), denoted by the sign & or dot. An equivalence relation is denoted by =, and negation by a bar or an apostrophe (") above the corresponding symbol.

Logic diagram has n inputs that correspond to n input variables X 1 , … X n and one or more outputs that correspond to output variables Y 1 …. Y m . Input and output variables can take two values X i = 1 or X i = 0.

The switching function (SF) of the logic circuit connects the input variables and one of the output variables using logical operations. The number of PF is equal to the number of output variables, while the PF can take the values 0 or 1.

Boolean operations. The following elementary operations (functions) are of the greatest practical interest.

Boolean multiplication (conjunction),

Logical addition (disjunction),

Boolean multiplication with inversion,

Logical addition with inversion,

Modulo 2 summation,

Equivalence.

Logic elements. There are digital integrated circuits corresponding to the basic logical operations. Logical multiplication corresponds to the logical element "AND". Logical addition corresponds to the logical element "OR". Logical multiplication with inversion - logical element "AND-NOT". Logical addition with inversion - logical element "OR-NOT". The inversion operation corresponds to the logical element "NOT". There are microcircuits that implement many other logical operations.

truth tables. The main way to set the PF is to compile a truth table, in which the value of the PF (0 or 1) is indicated for each set of input variables. The truth table for the logical element "NOT" (logical operation) is

Input X	Output Y

1.1. Study of the characteristics of the logical element "OR-NOT"

The scheme for studying the logical element "OR-NOT" is shown in fig. one.

On the diagram of Fig. 1 gate inputs "OR NO" connected to a word generator that generates a sequence of binary numbers 00, 01, 10 and 11. The right (lowest) binary digit of each number corresponds to the logical variable X1, the left (highest) - to the logical variable X2. The inputs of the logic element are also connected logic probes, which light up red when a logical "1" is received at this input. The output of the logic element is connected to a logic probe, which lights up red when a logic "1" appears at the output.

Building a research circuit for the logical element "OR-NOT"

Launch the program using the shortcut on the Windows desktop Electronics Workbench.

Construction of the circuit fig. 1 will be done in two stages: first, we will place it as shown in fig. 1 pictograms of elements, and then connect them in series.

1. Click the button

component libraries and instrumentation panels. From the logic element window that appears, pull out the logic element icon NOR("OR NO").

2. Click the button

From the window that appears, pull out the logical probe icons in sequence.

3. Expand the logic probes as shown in fig. 1. To do this, on the function bar, use the rotate button

4. Click the button

component libraries and instrumentation panels. From the indicator window that appears, pull out the icon word generator

5. Arrange the icons of the elements using the towing method as shown in fig. 1 and connect the elements according to the figure.

6. Double-click to open the front panel word generator.

On the left side of the panel word generator code combinations are displayed in hexadecimal code, and at the bottom - in binary.

7. Fill in the hexadecimal code window with code combinations, starting with 0 in the upper zero cell and then adding 1 in each subsequent cell. To do this, click on the button, in the window that appears, turn on the option Up counter and click on the button accept.

8. In the window Frequency set the pattern generation frequency to 1 Hz.

The sequences of binary numbers 00, 01, 10 and 11 correspond in hexadecimal code - 0, 1, 2, 3. Let's program the generator to generate the specified sequence of numbers periodically.

9. Dial in the window Final number 0003 click on the button cycle.

10. Start the simulation process using the switch. Watch for which combinations of input signals a "1" will appear at the output of the logic element. Clicking the button step, fill in the truth table for the element "OR-NOT" in the Report. Stop the simulation process with the switch.

11. Save the file in the folder with your Surname under the name Zan_17_01 .

This set allows you to study the logic of the main types of logic elements. The set is housed in a black plastic box sized 200 x 170 x 100 mm.

The installation contains four modules of standard size 155 x 95 x 30 mm. In addition, there should be connecting wires, but in the copy that the author dealt with, they were absent, but the instruction manual was preserved.

Logic element AND

The first module is a logic element And, a signal appears at its output only if the signal comes to both of its information inputs.

The standard module is a printed circuit board, which is closed on top with a transparent plastic cover, fixed with two screws.

The module is easily disassembled, which allows you to examine the circuit board of the device in detail. On the back side, the printed conductors are covered with an opaque plastic cover.

OR gate

The logical element is almost similarly arranged OR, a signal appears at its output provided that a signal arrives at any of its information inputs.

Gate NOT

Logic element NOT. The input and output signals of this element always have opposite values.

Trigger

Trigger- a logical device with two stable states, used as the basis for all kinds of devices requiring information storage.

In general, this digital electronics kit is similar to the Electronic Amplifier kit. Of course, the implementation of logical elements presented in the set is far from being the only one. In fact, logical elements are implemented here, as it was done in the 60s of the XX century. In this case, it is important that when working with this set, you can directly study the simplest circuit example underlying the very basis of digital semiconductor electronics. Thus, a separate logical element ceases to be a "black box" that operates on pure magic. A clearly visible and at the same time protected electrical circuit, this is just what you need to learn the basics of electronics. The author of the review is Denev.

A transistor is a semiconductor material component that allows you to control a sufficiently large electric current in a circuit by changing a smaller current at the control electrode.

There are bipolar and field-effect transistors. They differ in that in a bipolar transistor the charge transfer is carried out by both the main and minor charge carriers - holes and electrons. In field-effect transistors, charge transfer is carried out by only one type of carriers.

Synthesis and study of elements based on transistor-transistor logic (TTL). TTL circuits are based on npn bipolar transistors. Bipolar transistors are so named because the transfer of charges in them is carried out by two types of carriers - electrons and holes. The basic element of this technology is the NAND scheme. Logical multiplication is carried out due to the properties of a multi-emitter transistor.

OR-NOT element.

The implementation of the OR-NOT logic element on bipolar transistors is shown in Figure 1.1.

The OR-NOT logical function can be expressed with the AND and NOT functions using de Morgan's rules: the negation of a disjunction is the conjunction of negations. The circuit has two inverters VT1 and VT2, which are supplied using keys and voltages of opposite polarities. When a logical zero is applied to both inputs ("ground"), a discharge occurs in the p-region of the transistor, it becomes closed, while the current begins to flow through the transistors VT3, VT4, which perform the AND function, the voltage level is sufficient to provide a logical one. If at least one input is given a logical unit (“plus”), then there will be a voltage drop at one of the outputs of the inverters, the voltage at the output AND will not be enough to provide a logical unit.

Figure 1.1 - Logical element OR-NOT on bipolar transistors

Figure 1.2 - logical zeros are applied to the inputs of the OR-NOT element

Figure 1.2 shows a variant of the operation of the transistor circuit, when logical zeros are applied to the inputs, as a result, the output will be the value of a logical unit.

The OR-NOT element generates the following truth table (see Table 1.1):

Table 1.1 - Truth table of the element OR-NOT

Element NOT.

The NOT element on TTL is shown in Figure 1.3.

Figure 1.3 - Logic inverter (logical NOT function)

When the switch is set to the “plus” side, a small emitter current flows, this current allows you to open the transistor, a voltage drop occurs and the indicator does not light up, which corresponds to a logical zero. When the key is installed on the “ground” side, the blocking layer expands, the transistor resistance becomes much greater than the resistance of the resistor, the transistor is closed, there is no voltage drop, which corresponds to a logical unit.

The truth table of the NOT element (see tab. 1.2).

Table 1.2 - The truth table of the NOT element

When logical units are supplied by closing the keys and through the transistors, sufficient current flows around these keys and sufficient voltage is supplied to the inverting transistor at the input to open it, the current flows freely, the resistance of the inverting transistor is small, the voltage drops across the resistor at the inverter, the output is logical zero.

When the keys are either one or zero, or both zeros, the output voltage to the inverter is not enough to open it, its resistance is high and a high voltage level is formed on its collector, the output is a logical zero.

The scheme of the AND-NOT element with a complex inverter is shown in Figure 1.5.

Figure 1.5 - NAND element with a complex inverter

The truth table for this element corresponds to table 1.3.

This element consists of three stages: input (R1, VT1, VT2 - multi-emitter transistor model), phase-inverted (VT3, R2, R4) and output amplifier (VT4, VT5, VD3, R3).

When applying to the inputs x 1 and x 2 logical units, a collector current appears on the transistors VT1, VT2 and flows into the base of the transistor VT3, opening it. Part of the emitter current VT3 enters the transistor VT5, it opens, a low voltage level is set at the output y, while VT4 is closed (there is not enough voltage through the base-emitter junction VT4 and VD1). When at least one logical zero is applied, the collector current of transistors VT1, VT2 stops, VT3 and VT5 close, VT4 opens. Since VT5 is closed, a high voltage level is formed at the output.

Synthesis and study of elements on MIS transistors.

The development of computer circuitry based on MOS transistors began with the appearance in 1962 of a field-effect transistor with an induced channel. MOS transistor circuits are characterized by relative ease of manufacture, compactness, low power consumption, and high noise immunity to changes in supply voltage. MOS transistors have a metal-dielectric-semiconductor structure and are generally called MIS transistors. Since the dielectric is realized on the basis of SiO 2 oxide, the name MOSFETs (unipolar, channel) is used. The metal electrode to which the control voltage is supplied is called the gate (G), and the other two electrodes are called the source (I) and the drain (C). Current flows from source to drain. For the p-channel, the drain polarity is negative, and for the p-channel, it is positive. The main semiconductor plate is called lining (P). A channel is a near-surface conductive layer between source and drain, in which the amount of current is determined using an electric field.

There are no injection and diffusion processes in the channel. The operating current in the channel is due to the drift in the electric field of electrons in n-channels and holes in p-channels.

At zero value of the control voltage, the channel is absent and no current flows. The channel, which is formed under the action of an external control voltage, is called induced. The voltage at which the channel is formed is called the threshold voltage. The channel with the initial additional concentration of charges is called built-in. The speed of n-MOS transistors is 5-8 times higher than the speed of p-MOS transistors, since the mobility of electrons is much greater than holes. In MOS circuits, resistors are completely eliminated, their role is played by MOS transistors.

OR-NOT element.

The circuit of the OR-NOT element is shown in Figure 1.6.

Figure 1.6 - Element OR-NOT on MOSFETs

Transistor VT1 acts as a resistor since MOSFETs have a high resistance, in order for it to pass current, the source is connected to the positive pole of the source. When logical zeros are applied to transistors VT2 and VT3 at the same time, they close, they create a load after the transistor VT1, the level of this voltage corresponds to a logical one. The truth table of this element corresponds to table 1.1. If at least one or both logical units are applied to the input, one of the transistors VT2 and VT3 (or both) will open, a voltage drop will occur, the output will be a logical zero.

Element AND-NOT.

The AND-NOT element is shown in Figure 1.7.

Figure 1.7 - Element AND-NOT on MOSFETs

OR element.

Element I.

Synthesis and study of elements on CMDP structures.

OR-NOT element.

Element AND-NOT.

Synthesis and study of elements based on emitter-coupled logic (ECL).

The circuitry of the ESL elements is based on the use of a differential amplifier in the current switching mode. ESL elements appeared in 1967 and are currently the fastest among silicon-based semiconductor elements. Signal propagation delays in ESL elements have decreased to the subnanosecond range (approximately 1 ns).

The superfast operation of ESL elements is achieved through the use of an unsaturated mode of operation of transistors, output emitter followers, and small amplitudes of logical signals (about 0.8 V). The logical elements of the ESL have a paraphase output, which allows you to simultaneously receive the direct and inverse value of the implemented function. This gives a noticeable reduction in the total number of microcircuits in the equipment.

The features of ESL circuitry and its characteristics are:

Ability to combine the outputs of several elements to form new functions;

Ability to work on a low-resistance load due to the presence of emitter followers;

Low value of switching work and independence of power consumption from switching frequency;

High stability of dynamic parameters when changing temperature and supply voltage;

The use of a negative power supply and collector ground, which reduces the dependence of the output signals on noise in the power rails.

The disadvantages of ESL elements include the complexity of circuits, significant power consumption and difficulties in matching with TTL and TTLSH microcircuits.

Element I.

OR element.

Element AND-NOT.

OR-NOT element.

Synthesis and study of the NOT element on MIS transistors () in positive and negative logic.

SERGIEV POSAD

Lab #1

Logic functions, ELEMENTS and circuits

Objective

Study of logical functions, logic elements and circuits.

Devices and elements

Logic converter.

Word generator.

Voltmeter.

Logic probes.

Voltage source + 5 V.

The source of the "logic one" signal.

Two position switches.

Two-input elements AND, AND-NOT, OR, OR-NOT.

Microcircuits of the 74 series.

Brief information from the theory

Axioms of the algebra of logic

The variables considered in the algebra of logic can take only two values - 0 or 1. In the algebra of logic, an equivalence relation is defined (denoted by the sign =), the operation of addition (disjunction), denoted by the sign, multiplication (conjunction), denoted by the signs &, or a dot, and negations (or inversions), denoted by an underscore or an apostrophe."

The algebra of logic is defined by the following system of axioms:

x = 1 if x 0; x = 0 if x 1;

0&0 = 0; 1 1 = 1

1&1 = 1; 0 0 =0;

1&0 = 0&1 = 0; 0 1 = 1 0 = 1;

Boolean expressions

Logical expressions are usually written in conjunctive or disjunctive normal forms. In the disjunctive form, logical expressions are written as the logical sum of logical products, in the conjunctive form, as the logical product of logical sums. The procedure is the same as in ordinary algebraic expressions. Boolean expressions associate the value of a logical function with the values of boolean variables.

Logical laws and identities

When transforming logical expressions, the following logical laws and identities are used

Logic functions

Any logical expression composed of n variables using a finite number of logic algebra operations can be considered as some function of n variables. Such a function is called a logical function. In accordance with the axioms of the algebra of logic, the function can take on the value of 0 or 1, depending on the value of the variables. The function of n logical variables can be defined for 2 n values of variables corresponding to all possible values of n-bit binary numbers. The following functions of two variables x and at

f 1 (x, y) = x & y = x y = x - logical multiplication (conjunction),

f 2 (x, y) = x y - logical addition (disjunction),

f 3 (x,y) = = – Schaeffer stroke,

f 4 (x,y) = = – Pierce arrow,

f 5 (x,y) = x y = – addition modulo 2,

f 6 (x, y) = - equivalence.

Logic

A physical device that implements one of the operations of the algebra of logic or the simplest logical function is called a logical element. A circuit composed of a finite number of logical elements according to certain rules is called a logical circuit. The main logical functions correspond to the circuit elements that perform them.

truth table

Since the domain of definition of any function of n variables is finite (2 n values), such a function can be defined by a table of values f(i), which it takes at points i, where i= 0,…,2 n -1. Such tables are called truth tables. Table 1 presents the truth tables that define the above functions.

Table 1

	Variable values
	x	at	f1	f2	f 3	f4	f5	f6
0	0	0	0	0	1	1	0	1
1	0	1	0	1	1	0	1	0
2	1	0	0	1	1	0	1	0
3	1	1	1	1	0	0	0	1

Karnot maps

If the number of logical variables does not exceed 5-6, it is convenient to transform logical equations using Karnaugh maps. The purpose of the transformations is to obtain a compact logical expression (minimization). Minimization is performed by combining neighboring sets (terms). The merged sets must have the same feature values (all 0's or all 1's). For clarity, consider an example: let it be required to find a logical expression for the majority function f m of three variables x, y, z, described by the truth table shown in Table 2.

table 2

Majority function

№	x	y	z	f m
0	0	0	0	0
1	0	0	1	0
2	0	1	0	0
3	0	1	1	1
4	1	0	0	0
5	1	0	1	1
6	1	1	0	1
7	1	1	1	1

Here the row number is equal to the number i= 2 2 x+2 1 y+2 0 z formed by the values of the variables.

Let's make a Karnot map. It is something similar to a table, in which the names of columns and rows represent the values of variables, and the variables are arranged in such an order that when moving to an adjacent column or row, the value of only one variable changes. For example, in row xy of Table 3, the values of the xy variables can be represented by the following sequences 00,01,11,10 or 00,10,11,01. The table is filled with function values corresponding to combinations of variable values. The resulting table looks like the one shown below (Table 3).

Table 3

Carnot Map

majority function

xy z	00	01	11	10
0	0	0	1	0
1	0	1	1	1

On the Karnaugh map, we mark groups consisting of 2 k neighboring cells (2,4,8,) and containing 1, since they are described by simple logical expressions. Three ovals in the table define the logical expressions xy, xz, yz. Each oval joining two cells corresponds to logical transformations:

A compact expression describing a function is a disjunction of the logical expressions obtained with the help of Karn maps. As a result, we obtain an expression in disjunctive normal form

f m = xy v xz v yz .

If we combine 0, then we get the expression in conjunctive normal form

f m = (x v y)(x v z)(y v z).

When implementing the majority function of three logical variables, we obtain a circuit that, when three signals are applied to its inputs, will generate a signal at the output equal to the signal at most inputs (2 out of 3 or 3 out of 3). This scheme is used to restore the true value of the signals arriving at the 3 inputs, if an error is possible on one of the inputs.

To implement this function on the elements 2I-NOT, it is necessary to carry out the following transformations:

For DNF, a simpler expression is obtained, so it should be implemented. The corresponding circuit implementation is shown in fig. one.

Rice. one

STUDY OF LOGIC ELEMENTS

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Study of logical elements. Study of the logic of work. logical elements. Brief information from the theory

Logic element AND

OR gate

Gate NOT

Trigger

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